This application claims priority to Korean Patent Application No. 2004-54490, filed on Jul. 13, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly, to a local sense amplifier with improved operating frequency in a semiconductor memory device.
2. Description of the Related Art
Increase in chip size of a semiconductor memory device results in increased length and thus capacitance of a data line. Such increased capacitance results in higher delay for transmission of data through the data line. To address this problem, a current sense amplifier, which is not affected by the capacitance of the data line, is used in a semiconductor memory device.
The current sense amplifier advantageously does not create a voltage difference on the data lines. Thus, the data lines need not be synchronized, even when different data are consecutively transmitted. Also, the current sense amplifier operates normally even when the semiconductor memory device operates at high speed.
However, the current sense amplifier must be consistently supplied with a current to make a virtual short along an input/output (I/O) line. Thus, the current sense amplifier requires more current to operate than a voltage sense amplifier. For this reason, the current sense amplifier may not be practical for a memory device used in mobile communication equipment that must operate at high speed with less power consumption.
When a voltage sense amplifier is used in a memory device that has a hierarchical I/O line structure, a local sense amplifier is installed between local I/O lines and global I/O lines to increase the operating speed of the memory device. FIG. 1 shows a circuit diagram of a conventional local sense amplifier 100. FIG. 2 shows a timing diagram of signals during operation of the local sense amplifier 100 of FIG. 1.
The local sense amplifier 100 includes read transistors RTR1, RTR2, RTR3, RTR4, and RTR5 that transmit read data, write transistors WTR1 and WTR2 that transmit write data, and precharge transistors PTR1, RTR2, and PTR3 that precharge a pair of local I/O lines LIO and LIOB.
During a read operation, a column select line signal CSL is activated to a logical high level. The activated CSL signal allows transmission of data amplified by a bit-line sense amplifier (not shown) to the pair of local I/O lines LIO and LIOB. The data transmitted to the pair of local I/O lines LIO and LIOB is amplified by the local sense amplifier 100 and transmitted to a pair of global I/O lines GIO and GIOB.
The time at which the local sense amplifier 100 amplifies and transmits the data to the pair of global I/O lines GIO and GIOB is controlled by a read control signal PBLK_R. When the read control signal PBLK_R is activated to the logical high level, the read transistors RTR1, RTR2, and RTR5 are turned on to transmit the amplified data to the pair of global I/O lines GIO and GIOB.
As shown in FIG. 2, the read control signal PBLK_R is activated at almost the exact same time as the column select line signal CSL. The read control signal PBLK_R activates a respective local sense amplifier corresponding to a memory block selected by a word line.
That is, only a local sense amplifier located in a region of a selected memory block operates. When the read control signal PBLK_R is activated after activation of the column select line signal CSL, data access is delayed between activation of the CSL signal and the activation of the read control signal PBLK_R.
In contrast, when the read control signal PBLK_R is activated before activation of the CSL signal, data is transmitted through the local sense amplifier 100 before valid data is applied on the pair of local I/O lines LIO and LIOB. Thus, invalid data is transmitted to the pair of global I/O lines GIO and GIOB with unnecessary power consumption.
Accordingly, in the conventional local sense amplifier 100, the read control signal PBLK_R and the CSL signal should be activated at the exact same time for proper operation.
FIG. 3 is a block diagram of a conventional memory array 300. The conventional memory array 300 includes a row decoder 310, a column decoder 320, and a plurality of memory blocks MB. Although not shown in FIG. 3, each local sense amplifier 100 of FIG. 1 is installed at a junction between a respective bit-line sense amplifier (not shown) and a respective sub word line driver (not shown) of a respective memory block MB.
Referring to FIG. 3, using a row address, a read control signal PBLK_R is transmitted in the direction of a word line WL after a predetermined delay, while a column select line signal CSL is transmitted perpendicular to the word line WL. Thus, even if the memory array 300 is designed such that both the read control signal PBLK_R and the column select line signal CSL are activated at exactly the same time for a memory block MB1, these signals PBLK_R and CSL are inevitably activated at different times within another memory block MB2.
Such signals PBLK_R and CSL are activated at different times within different memory blocks because of differences in the delay of such signals PBLK-R and CSL reaching each memory block. That is, it is difficult to activate the column select line signal CSL and the read control signal PBLK_R simultaneously within every memory block MB. Consequently, the operating frequency range of the memory array 300 is limited.
This problem becomes worse for a precharge control signal /PRE that precharges the pair of local I/O lines LIO and LIOB. When read operations are continuously performed, one column select line signal CSLi is deactivated and another column select line signal CSLi+1 is activated.
Generally, the precharge control signal /PRE pulse needs to precharge the pair of local I/O lines LIO and LIOB after the column select line signal CSLi is deactivated and before the next column select line signal CSLi+1 is activated. Thus, the precharge control signal /PRE pulse must be generated with sufficient pulse width precisely between the activation of the column select line signal CSLi and the next column select line signal CSLi+1.
When the precharge control signal /PRE pulse is generated before deactivation of the prior column select line signal CSLi, a current path is formed between the pair of local I/O lines LIO and LIOB and a bit-line sense amplifier (not shown), thereby causing unnecessary power consumption. On the other hand, when generation of the precharge control signal /PRE pulse overlaps activation of the next column select line signal CSLi+1, a current path is formed between the bit-line sense amplifier and precharge transistors PTR1, PTR2, and PTR3 along the pair of local I/O lines LIO and LIOB of the local sense amplifier 100. The current path causes unnecessary power consumption, and moreover, delays data access through the local sense amplifier 100.
The precharge control signal /PRE is transmitted in the direction of the word line WL, but the column select line signal CSL is transmitted perpendicular to the word line WL. Thus, even if the precharge control signal /PRE pulse is generated simultaneously with activation of the column select line signal CSL within the memory block MB1, the precharge control signal /PRE pulse may not be generated simultaneously with activation of the column select line signal CSL within the another memory block MB2. That is, it is difficult to generate the precharge control signal /PRE pulse with simultaneous activation of the column select line signal CSL within every memory block MB. Consequently, the operating frequency range of the memory array 300 is limited.
FIG. 4 illustrates a discrepancy between the time when a precharge control signal /PRE pulse is generated and the time when a column select line signal CSL is activated. There is a time delay D between the activated column select line signal CSL reaching the first memory block MB1 and the second memory block MB2. Thus, if the precharge control signal /PRE pulse is generated when the column select line signal CSL is deactivated at the first memory block MB1, the precharge control signal /PRE pulse may be generated when the column select line signal CSL is still activated at the second memory block MB2.
Similarly, during a write operation, a write control signal PBLK_W is activated to connect the pair of global I/O lines GIO and GIOB and the pair of local I/O lines LIO and LIOB of FIG. 1. Since the pair of global I/O lines GIO and GIOB reach full swing during the write operation, it is possible to transmit data using only the write transistors WTR1 and WTR2 of FIG. 1 without an additional amplifier.
The write control signal PBLK_W should also be activated simultaneously with the column select line signal CSL at each memory block. Therefore, the time when the write control signal PBLK_W is activated must be adjusted precisely. However, since the write control signal PBLK_W is also transmitted perpendicular to the column select line signal CSL, it is difficult to activate the write control signal PBLK_W and the column select line signal CSL simultaneously at each memory block.